(China (Mainland))
Product Summary
The 74LVC1G04GW is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 or 5 V devices. These features allow the use of these devices in a mixed 3.3 and 5 V environment. Schmitt trigger action at all inputsmakes the circuit tolerant for slower input rise and fall time. This 74LVC1G04GW is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G04GW provides the inverting buffer.
Parametrics
74LVC1G04GW absolute maximum ratings: (1)supply voltage: -0.5 to +6.5 V; (2)input diode current, VI <0: -50 mA; (3)input voltage, note 1: -0.5 to +6.5 V; (4)output diode current, VO >VCC or VO <0: ±50 mA; (5)output voltage: active mode; notes 1 and 2, -0.5 to VCC + 0.5 V; Power-down mode; notes 1 and 2, -0.5 to +6.5 V; (6)output source or sink current, VO =0 toVCC: ±50 mA; (7)VCC or GND current: ±100 mA; (8)storage temperature: -65 +150 ℃; (9)power dissipation per package for temperature range from - 40 to +125℃: 250 mW.
Features
74LVC1G04GW features: (1)Wide supply voltage range from 1.65 to 5.5 V; (2)High noise immunity; (3)Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V); JESD8-5 (2.3 to 2.7 V); JESD8B/JESD36 (2.7 to 3.6 V); (4)±24 mA output drive (VCC = 3.0 V); (5)CMOS low power consumption; (6)Latch-up performance ≤250 mA; (7)Direct interface with TTL levels; (8)Inputs accept voltages up to 5 V; (9)Multiple package options; (10)Specified from -40 to +125℃.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||||||||
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 74LVC1G04GW,125 |
NXP Semiconductors |
Inverters INVERTER BUFFER PICOGATE |
Data Sheet |
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74LVC1G04GW,165 |
NXP Semiconductors |
Inverters SINGLE INVERTER |
Data Sheet |
Negotiable |
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74LVC1G04GW-R |
NXP Semiconductors |
Inverters SINGLE INVERTER |
Data Sheet |
Negotiable |
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