Product Summary

The TMS320DM6467TZUTD1 leverages TI DaVinci technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. It enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the TMS320DM6467TZUTD1 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S core.

Parametrics

TMS320DM6467TZUTD1 absolute maxing ratings: (1)Supply voltage ranges: Core (CVDD, DEV_CVDD, AUX_CVDD)(2): -0.5 V to 1.5 V; I/O, 3.3V (DVDD33, USB_VDDA3P3)(2): 0 V to 3.8 V; I/O, 1.8V (DVDDR2, PLL1VDD18, PLL2VDD18, DEV_DVDD18, AUX_DVDD18, USB_VDD1P8)(2): 0 V to 2.6 V; (2)Input and Output voltage ranges: V I/O, 3.3-V pins (except PCI-capable pins): –0.3 V to 3.8 V/–0.3 V to DVDD33 + 0.3 V; V I/O, 3.3-V pins PCI-capable pins: –0.5 V to 4.2 V/–0.5 V to DVDD33 + 0.5 V; V I/O, 1.8 V: –0.3 V to 2.6 V/–0.3 V to DVDD18 + 0.3 V; (3)Operating case temperature range, Tc: (default): 0℃ to 85℃; (4)Storage temperature range, Tstg (default): –65℃ to 150℃.

Features

TMS320DM6467TZUTD1 features: (1)High-Performance Digital Media SoC: 594-MHz C64x+. Clock Rate; 297-MHz ARM926EJ-S. Clock Rate; Eight 32-Bit C64x+ Instructions/Cycle; 4752 C64x+ MIPS; Fully Software-Compatible With C64x /ARM9; (2)Advanced Very-Long-Instruction-Word (VLIW)TMS320C64x+. DSP Core: Eight Highly Independent Functional Units; Load-Store Architecture With Non-Aligned Support; 64 32-Bit General-Purpose Registers; Instruction Packing Reduces Code Size; All Instructions Conditional; Additional C64x+. Enhancements; (3)C64x+ Instruction Set Features: Byte-Addressable (8-/16-/32-/64-Bit Data); 8-Bit Overflow Protection; Bit-Field Extract, Set, Clear; Normalization, Saturation, Bit-Counting; Compact 16-Bit Instructions; Additional Instructions to Support Complex Multiplies.

Diagrams

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